Today's deep-submicron ICs make it possible for designers to mount components with rise and fall times in the hundreds of picoseconds, and to design densely packed boards with clock rates of more than 100 MHz. Use of these high-speed ICs makes crosstalk, timing delays, EMI, and impedance issues significant ones in any PCB design. In single-board systems, currently available board layout and analysis tools generally meet these challenges satisfactorily, but when a single system includes multiple high-speed boards, EMI, crosstalk, and timing delay issues are compounded to new levels of complexity.

To cite only one example, sub-nanosecond edge rates might not even be a cause for concern within a single board, but in multi-board systems such considerations become much more complicated, and the potential for problems is increased exponentially. In addition, correcting design flaws once a board has reached layout is time-consuming and costly in any event, but in multi-board systems the delay in time-to-market and cost is greatly increased because of the complexity of the system and the greater potential for design errors.

The key to anticipating and identifying these issues is pre-layout analysis. By simulating at the system level, designers can anticipate and identify potential issues and modify individual board designs. And by moving from a post-layout validation to a pre-layout approach designers can accelerate time to market by validating all possible system configurations and ensuring interoperability. The result will be lower costs due to fewer design flaws, and higher customer satisfaction.

Hardware, software, and system designers should collaborate from the very beginning of the project. Involving hardware and software engineers at the pre-layout stage minimizes the risk of uncovering problems at the post-layout or prototype stages, when they are most expensive to fix. This collaboration, using simulation tools such as Viewlogic Systems' eArchitect, allows systems designers to concurrently analyze various hardware and software architectures at the beginning of their designs.

Finding the right tool set

Just as important as pre-layout analysis is the use of an integrated suite of signal integrity, EMI, and static timing tools that have the capability to track down and identify problems in high-speed multi-board systems, and to validate multiple configurations before prototype.

Such a tool suite needs to meet a number of requirements: It should be able to analyze designs in widely used CAD database formats such as Cadence Design's Allegro, Mentor Graphics' Boardstation, PADS' PowerPCB, and Zuken-Redac's Visula. It also should support any combination of IBIS, vendor SPICE, or measurement data as models of I/O cells. Since connector design is an integral part of system-wide analysis, the suite needs to accept models for connectors as either single-line or coupled groups. For timing analysis, the tools must work with timing models for components, ASICs, and FPGAs. System-wide EMI analysis also requires the definition of system clocks and enclosures.

The analysis of a multi-board system must begin at the design capture stage. Keeping in mind the objectives of maximum flexibility and margin, the designer must set up rules and constraints to eliminate, as far as possible, signal integrity, EMI, and timing issues in data generated by the backend system. Such rules can be defined with tools such as Viewlogic Systems' ISIS PreVue, a graphical what-if analysis tool that designers can use to simulate topologies, signal constraint, and termination strategies, as well as to play with electrical properties that affect signal timing and integrity. (See Figure 1.)

The first step in this process is to capture the critical netlists, such as bus signals that go from one board to another. The designer then calculates the space in which those nets operate using a tool such as Viewlogic Systems' ePlanner, which predefines acceptable impedance ranges, trace lengths, and other criteria so that signal integrity or delay will not be degraded. For example, in a three-board system a designer might set constraints for a particular 75-ohm trace to run somewhere between two to four inches on board one, three to five inches on board two, and two to seven inches on board three. When simulation confirms that the circuit will operate to spec if these various design constraints are met, they can be turned over to the PCB CAD environment in the form of a constrained netlist.

The next step is to review the crucial nets that run across boards at the board placement stage. The process begins with the definition of an initial hierarchy description file using multiple board instances. Then interconnects are defined by identifying which connectors plug into each board. If any cables are to be used, they must be modeled and inserted into the design between the boards it interconnects.

The design hierarchy data can be used to automatically generate a system-wide netlist and transmission line parameters, which allows the designer to assign I/O and timing models and insert connector models.

When the initial placement is complete, the designer runs a signal integrity analysis on critical nets that cross board boundaries. Then, timing constraints can be verified with a static timing analyzer, using back-annotated data from the signal integrity tool.

In a multi-board system the signal integrity tool must be one that can connect multiple PCB databases and perform system-wide analyses. An example of such a tool is Viewlogic Systems' XTK, which is integrated with ISIS preVUE. To help define the rules for the routing of nets and the kinds of drivers needed, the tool also must provide pre-layout analyses that prototype critical clock and data network signal topologies. It must compare signal quality for multiple termination strategies to determine the best possible solution. And finally, it must resolve board stack issues and river strength requirements. These capabilities will allow the designer to develop design rules for line length and spacing to meet crosstalk specifications at the maximum clock rate. Sweep and Monte Carlo analyses are useful to illustrate how variations in components and the environment will impact electrical performance and affect manufacturability.

The signal integrity tool should be able to perform a complete extraction, including inductance and capacitance matrices to measure crosstalk effects, insulator dielectric loss, line resistance, and skin-effect loss. It's important, too, that the tool be able to handle large, complex systems and still perform simulations extremely quickly. (See Figure 2.)

Once the layout is completed, the signal integrity tool should allow designers to quickly review a design without taking the time to look at individual waveforms. Therefore it should automatically generate violation reports that can be customized to user-specified limits. Such reports might include signal delay, undershoot and overshoot, non-monotonic edges, incorrect loading, and mismatched logic thresholds.

Typical multi-board designs run at clock rates of 100 MHz and higher, creating complex circuit topologies that combine microprocessors, rams, FPGAs, ASICs, and random logic. Timing verification that uses the interconnect delay data generated in the signal integrity analysis is a critical step in the system design process

For this task designers need a static timing analysis tool, such as Viewlogic's Blast (shown in Figure 3), that identifies all setup and hold violations by tracing every signal delay path in a multi-board design. It also must verify all timing margins quickly and accurately, and import actual interconnect delays from a signal integrity tool for post-layout analysis. The static timing analysis tool should display not only clocks and data paths, but also basic information on nets, parts, and models; detailed data on the calculated timing margin; multi-cycle paths applied; and delay values. These tools also can provide what-if capabilities that allow the designer to identify possible solutions easily and quickly.

The routing process begins once all signal integrity and timing issues on cross-board nets have been rectified. Keep in mind that signal integrity analysis and timing verification are iterative processes that can be continuously performed and updated as routing progresses -- very important in critical areas of multi-board design. For example, verifying that design constraints are met after routing each individual bus net allows the designer to gradually tighten up design rules by adding physical constraints that couldn't have been added at the logical design stage. Once problems are fixed and new design rules are input, then the designer can proceed to route the entire bus.

Preliminary EMI analysis can start as soon as the routed data on critical nets is available, and FCC requirements can be checked. High-speed clock or data bus nets that will be doing a lot of transitioning are especially important to check, as they are most susceptible to EMI issues.

Once all the signal integrity problems are rectified a system-wide EMI analysis should be performed using optional enclosure definitions (see Figure 4). EMI tools that offer 3-D analysis capabilities, such as Viewlogic Systems' XTK, can be used to simulate EMI radiation for boards and connecting cables inside a product enclosure. Some tools feature a full-wave 3-D field solver to ensure accurate system-level simulation.

Cable-induced common-mode radiation can be a problem in multi-board systems. EMI visualization software can be used to observe animated versions of EMI radiation both inside and outside the system enclosure. Various system-level changes can be simulated to what changes are need to reduce undesired radiation levels. Once the EMI issues are resolved, it is essential to go back and revalidate signal integrity simulation.

The designer should perform an exhaustive signal integrity analysis of the whole system once the routing is completed. This is followed by timing verification, using a timing stack report to locate any tight timing margins. Partial rerouting of critical signals can enhance design margins and improve the reliability of the end product.

Finally, an Internet-enabled component information tool, such as Viewlogic Systems' DxDataBook, assures that each member of the design team uses the same component database, avoiding costly mistakes that may not be discovered until late in the project.

High-performance multi-board systems will pose greater and greater design challenges as clock rates get higher and faster, and faster signal edges are required. But designers can meet these challenges by taking advantage of integrated system analysis tools, and by simulating signal integrity, timing, and EMI issues at the system level rather than post-layout. Not only can they avoid time-consuming and costly rebuilds, but the economies of pre-layout analysis will allow them to push the performance envelope to its limits.